feat: add 32-bit assembly checksum backends (ARM, x86, RV32, MIPS32, PowerPC) #27

Merged

meigoc merged 2 commits from feat/arch32-asm into main

2026-07-18 10:54:43 +00:00

meigoc commented

2026-07-18 01:01:40 +00:00

(Migrated from github.com)

arch/arm/ — ARM (AArch32 / ARMv7)
arch/x86/ — x86 (i386 / IA-32)
arch/riscv32/ — RISC-V (RV32)
arch/mips/ — MIPS32 (MIPS32r2)
arch/powerpc/ — PowerPC (32-bit)

Each backend implements the ABI the C drivers already dispatch to
(apg_<algo>_hw_supported / apg_<algo>_transform_hw / apg_crc32_update_hw)
and is selected at build time in meson.build via host_machine.cpu_family().
Message words are assembled byte-wise (endian-independent) and symbol addressing
is position-independent, so the backends link cleanly into the shared library.

Type of Change

New feature

Checklist

Code compiles without errors
Tests pass locally
Code follows project style guidelines
Documentation updated (if needed)
Commit messages follow conventional commits format

Testing

For every target the library's own C checksum drivers were built against the new
assembly and the full CRC-32, MD5 and SHA-256 were computed over test vectors
(empty input, sub-block, exact block, multi-block, odd tails, all-byte-value
data), with digests compared byte-for-byte against independent reference values.
Verified under QEMU user-mode on arm, i386, riscv32, mipsel, big-endian
mips, and powerpc (big-endian MIPS and PowerPC confirm endian independence).

PIC-safety was checked by assembling each backend with -fPIC and linking a
shared object with -Wl,-z,text. Native x86_64 build and the existing test
suite continue to pass unchanged.

New cross-*.txt files and CI coverage were added: an arch-asm job that
assembles and PIC-links every 32-bit backend, plus a full armhf cross job.

Additional Notes

Base integer instructions only (no crypto extensions), matching the existing
mips64 backend; -march is raised only where encodings require it (armv7-a
for movw/movt, mips32r2 for rotr).

Adds optimized scalar assembly implementations of the checksum backend (CRC-32, MD5, SHA-256) for five 32-bit architectures, extending the existing 64-bit backends (x86-64, aarch64, riscv64, mips64) to 32-bit targets: - `arch/arm/` — ARM (AArch32 / ARMv7) - `arch/x86/` — x86 (i386 / IA-32) - `arch/riscv32/` — RISC-V (RV32) - `arch/mips/` — MIPS32 (MIPS32r2) - `arch/powerpc/` — PowerPC (32-bit) Each backend implements the ABI the C drivers already dispatch to (`apg_<algo>_hw_supported` / `apg_<algo>_transform_hw` / `apg_crc32_update_hw`) and is selected at build time in `meson.build` via `host_machine.cpu_family()`. Message words are assembled byte-wise (endian-independent) and symbol addressing is position-independent, so the backends link cleanly into the shared library. ## Type of Change - [x] New feature ## Related Issues - NurOS-Linux/libAPG#21 - NurOS-Linux/libAPG#22 - NurOS-Linux/libAPG#23 - NurOS-Linux/libAPG#24 - NurOS-Linux/libAPG#25 ## Checklist - [x] Code compiles without errors - [x] Tests pass locally - [x] Code follows project style guidelines - [x] Documentation updated (if needed) - [x] Commit messages follow conventional commits format ## Testing For every target the library's own C checksum drivers were built against the new assembly and the full CRC-32, MD5 and SHA-256 were computed over test vectors (empty input, sub-block, exact block, multi-block, odd tails, all-byte-value data), with digests compared byte-for-byte against independent reference values. Verified under QEMU user-mode on `arm`, `i386`, `riscv32`, `mipsel`, big-endian `mips`, and `powerpc` (big-endian MIPS and PowerPC confirm endian independence). PIC-safety was checked by assembling each backend with `-fPIC` and linking a shared object with `-Wl,-z,text`. Native `x86_64` build and the existing test suite continue to pass unchanged. New `cross-*.txt` files and CI coverage were added: an `arch-asm` job that assembles and PIC-links every 32-bit backend, plus a full `armhf` cross job. ## Additional Notes Base integer instructions only (no crypto extensions), matching the existing mips64 backend; `-march` is raised only where encodings require it (`armv7-a` for `movw/movt`, `mips32r2` for `rotr`).

AnmiTaliDev (Migrated from github.com) reviewed

2026-07-18 01:01:40 +00:00

AnmiTaliDev (Migrated from github.com) reviewed

2026-07-18 01:01:40 +00:00